RVV: Variable Length, Variable Pain

RISC-V Vector (RVV) is one of the most discussed and anticipated extensions of the RISC-V architecture. Many programmers are eagerly awaiting chips with RVV support in hopes of speeding up their code, but the price of this acceleration is not always obvious.

In this talk, we will analyze code examples that appear fast but can actually destroy performance. For better understanding, we'll need to go below the assembly level and get our hands dirty with pipeline hazards. We'll also take on the role of a CPU verification engineer and explore the challenges that an average engineer faces when working with RVV on silicon.

As a result, we'll gain an understanding of what RVV is, when it should be used, and how to combine it with scalar instructions for maximum efficiency.