Sergey Yakushkin

Director of software engineering at Syntacore, company developing microprocessor technologies based on RISC-V architecture and co-founder of RISC-V International. Open-source core SCR1 and toolchain are one of the most popular RISC-V processor projects at GitHub. Graduated from SPbSU, worked at Intel, Huawei, Synopsys on C/C++/OpenCL compilers, toolchains, debugging and simulation tools, designed domain-specific programming and architecture description languages. Published papers at international compiler and EDA conferences such as LLVM, DATE, DAC, HPCA.